仕事ーVHDL データタイプとオブジェクト

・ 配列タイプ

type BYTE is array (7 downto 0) of std_logic;
type MEMORY is array (0 to 255) of BYTE;
type std_logic_vector is array (integer range <>) of std_logic;

signal INBUS : BYTE;
signal SIG_A : std_logic_vector(15 downto 0);
signal N_100 : std_logic_vector(0 to 31);

・ 定数

constant WIDTH : integer := 8;
constant X : std_logic := 'X';

signal A : std_logic := X;
. . .
if (SIG'length > WIDTH) then

・ 信号と信号代入
signal A, B : BIT;
signal CLK : std_logic := 'U';
signal INIT : integer := 1;
signal VEC : std_logic_vector(15 downto 0);
architecture A of E is
signal A, B, C, S : std_logic;
signal F, G : std_logic;
signal CK, D, Q, R : std_logic;
begin
F <= (A and B) or C; 　　　 -- 並行信号代入文
G <= A when S = '1' else B; -- 条件信号代入文

process begin
wait until CK'event and CK = '1';
Q <= D after 0.6 ns; 　-- プロセス内の信号代入文
end process;
end A;

・ 変数と変数代入

process (S1, S2)
variable V1, V2: std_logic;
begin
V1 := S1 and S2;
V2 := S1 xor S2;
F <= V1 & V2;
end process;

・ A'stable <(時間)>

属性が実行された時刻において、指定された時刻だけ値が変化していなければTUREを、それ以外にはFALSEを戻します。

process begin
wait until CLOCK'event and CLOCK='1';
if not DATA'stable(1.4 ns) then
assert FALSE
report "Warning: Setup Time Violation"
severity Warning;
end if;
end process;